Phase-locked loops (PLLs) can provide precise generation and alignment of timing for a wide variety of applications. Digital phase-locked loops (DPLLs) are a viable alternative to traditional PLLs, in which a digital loop filter can be utilized to replace analog components. Further, time to digital converters (TDCs) can operate to digitally encode a phase error between reference and divider outputs. In ring oscillator based TDCs, power consumption and phase noise increase with measured time. The measure time of all digital phase locked loops (ADPLLs) is thus kept as small as possible to avoid power consumption and phase noise penalty. Because TDCs typically measure positive times, an additional TDC offset is normally introduced in front of a digital loop filter of the ADPLL, in which the TDC offset is chosen to give a margin for a multi-modulus divider (MMD) induced edge variation. A need exits therefore to overcome measure time induced power and phase noise penalty, while pursuing high resolution and high linearity in the TDC time-to-digital mapping characteristic with low power and low area in the implementation.